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HSDL - 7002
IrDA 3/16 Encode/Decode Integrated Circuit in QFN Package
Data Sheet
Description
The HSDL-7002 modulates and demodulates electrical pulses from HSDL-3201 IrDA transceiver module and other IrDA compliant transceivers. The HSDL-7002 can be used with a microcontroller/microprocessor that has a serial communication interface (UART). Prior to communication, the processor selects the transmission baud rate. Serial data is then transmitted or received at the prescribed data rate. The HSDL-7002 consists or two state machines - the SIR (Serial InfraRed) Encode and SIR Decode blocks. It also contains a sequential block Clock Divide that synthesizes the required internal signal. The HSDL-7002 can be placed into the Internal Clock Mode or External Clock Mode. An external crystal is needed for the Internal Clock Mode. In applications where the external 16XCLK signal is provided, a crystal is not needed. There are two data transmission modes. Data can be transmitter and received in either a standard 3/16 modulation mode or a 1.63 s pulse mode.
Features
* Fully Compliant to IrDA Physical Layer Specification 1.4 from 9.6 kbit/s to 115.2 kbit/s (SIR) * Interfaces with IrDA Compliant IR Transceiver * Miniature Module Size with 16-pin Quad-Flat-No Lead (QFN) Package Height : 0.8 mm Length : 4.0 mm Depth : 4.0 mm * Used in Conjunction with Standard 16550 UART * Transmits/Receives either 1.63 s or 3/16 Pulse Mode * Internal or External Clock Mode * Programmable Baud Rate 2.7 - 5.5 V Operation * Lead Free and Green Product
Applications
* Interfaces with IrDA Transceiver in: * Telecom Applications: Mobile Phones Modems Pagers Fax Machines * Computer Applications: Notebook Computers Desktop PCs Dongles or other RS-232 adapters PDAs Printers * Handheld Data Collection: Industrial Medical * Transportation
/TXD IR_TXD /NRST
SIR Encode
SIR Decode
/IR_RXD RXD
HSDL-7002 A0 A1 A2 16XCLK PULSEMOD CLK_SEL Clock Divide
Figure 1. Block Diagram of HSDL-7002
Pin 15
Pin 14
PIN #1 CORNER
Pin 16
Pin 13
Order Information
Part Number Packaging Type HSDL-7002 Tape and Reel Quantity 2500
Pin 1 Pin 2 Pin 3 Pin 4
Pin 12 Pin 11 Pin 10 Pin 9
Marking Information
The unit is marked with A7002 and `yyww' on the chip. yy = year ww = work week
Pin 6
Pin 7
Figure 2. HSDL-7002 Pin Configuration
I/O Pins Configuration Table
Function 1 Negative edge triggered input signal that is normally tied to the SOUT signal of the UART (serial data to be transmitted). Data is modulated and output as IR_TXD. 2 RXD Digital Out Output signal normally tied to SIN signal of a UART (received serial data). RXD is the demodulated output of IR_RXD. 3 A0 Digital In Clock Multiplex Signal 4 A1 Digital In Clock Multiplex Signal 5 A2 Digital In Clock Multiplex Signal 6 CLK_SEL Digital In Used to activate either the internal or external clock. A high on this line activated the external clock (16XCLK) and a low activates the internal clock. When the external clock is activated, the internal oscillator is put in POWERDN mode. 7 GND Chip Ground 8 NRST Digital In Activate low signal used to reset the IrDA SIR Encode & Decode state machine. This signal can be tied to POR (Power-On-Reset) or Vcc. 9 IR_RXD Digital In Input from SIR optoelectronics. Input signal is a 3/16th or 1.63 ms pulse that is demodulated to generate RXD output signal. 10 IR_TXD Digital Out This is the modulated TXD signal. 11 PULSEMOD Digital In A high level on this input put the chip into the monoshot transmit mode. In (with pull down) this mode, when there is a negative transition on the TXD input, a rising edge on the internal transmit modulation state machine will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a 3.6864 MHz crystal, this corresponds to 1.63 ms. This mode cannot be used in conjunction with the 16XCLK clock. It is meant to be used with the external crystal clock. By default, this input pin is pulled to GND 12 POWERDN Digital In A high on this input put only the internal oscillator cell in POWERDN mode. (with pull down) The cell is normally not powered down. 13 OSCOUT Analog Out Oscillator Output 14 OSCIN Analog In Oscillator Input 15 Vcc Power 16 16XCLK Digital In Positive edge triggered input clock that is set to 16 times the data transmission baud rate. The encode and decode schemes require this signal. The signal is usually tied to a UART's BAUDOUT signal. The 16XCLK may be provided by application circuitry if BAUDOUT is not available. This signal is required when the internal clock is not used.
Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLK_SEL pin is asserted high (external clock select) the oscillator is automatically put in powerdown mode, or whenever the POWERDN pin asserted high.
Name TXD
Pin 5
Type Digital In
2
Pin 8
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Output Current Power Dissipation [1] Input/Output Voltage [2] Power Supply Voltage Electrostatic Protection Symbol TS TA IO PMAX VI /VO VCC VESD -0.5 -0.5 Min. -65 -40 -20 Max. +150 +85 15 0.46 Vcc+0.5 7.0 4000 Units C C mA W V V V
Note: 1. All pins are protected from damage to static discharge by internal diode clamps to Vcc and GND.
Switching Specifications (Vcc = 2.7 to 5.5 V, TA = -20 to +85C)
Parameter Propagation Delay Time [1] Output Rise Time [2] Output Fall Time [3] Output Capacitance on Output Pads Used for Simulation Symbol Min. tpd trise tfall COUT 13 6 12 5 22 11 14 10 Typ. Max. 45 24 12 16 11 50 Units ns ns ns pF VCC = 2.7 V, CL = 50 pF VCC = 5.5 V, CL = 50 pF VCC = 2.7 V, CL = 50 pF VCC = 5.5 V, CL = 50 pF Conditions
Notes: 1. Propagation Delay Time in the output buffer is the time taken from the input passing Vcc/2 to the time of the output reaching Vcc/2 with 50 pF as the output load. 2. The Ouput Rise Time is the time taken for the outputs (RXD, IR_TXD) to rise from 10% of the original value to 90% of the final value. 3. The Output Fall Time is the time taken for the outputs (RXD, IR_TXD) to fall from 90% of the original value to 10% of the final value.
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Recommended Operating Conditions (Vcc = 2.7 to 5.5 V, TA = -20 to +85 C)
Parameter Supply Voltage Input Voltage Ambient Temperature High Level Input Voltage Low Level Input Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Static Power Dissipation Dynamic Power Dissipation Static Current Consumption Dynamic Current Consumption Max Clk Frequency (16XCLK) [1] Minimum Pulse Width (IR_TXD) [2] Pulse Width on Monoshot (IR_TXD and IR_RXD) Value of Pulldown Resistor used on POWERDN & PULSEMOD input pins Trigger Low Level Input Voltage (For NRST input pin) Trigger High Level Input Voltage (For NRST input pin) Symbol VCC VI TA VIH VIL VOH VOL VOH VOL PSTAT PDYN ISTAT IDYN f16XCLK tmpw tmpw RDWN VIL_TRIG 1628 1628 400 213 0.93 2.11 460 237 0.96 2.14 1.69 3.23 510 260 0.98 2.15 1.70 3.25 1.08 2.45 5.1 0.1 0.61 16.5 50 100 3 3 2 Min. 2.7 0 -20 0.7 VCC 0 2.6 0.1 Typ. 5.0 Max. 5.5 VCC +85 VCC 0.3 VCC Units V V C V V V V V V mW mW mA mA MHz ns ns kW V V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V IOH = 2 mA VCC = 2.7 V IOL = 2 mA VCC = 5.5 V IOH = 2 mA VCC = 2.7 V IOL = 2 mA Conditions
VIH_TRIG 1.68 3.22
Notes: 1. IrDA Parameter. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7002's internal state machine. Under normal circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 MHz. This product can operate at higher clock rates, but the above is the recommended rate. 2. The Maximum Pulse Width (tmpw) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RXD pulse). As per the IrDA Physical Layer Specification 1.4, the minimum pulse of the IR_TXD and IR_RXD pulses should be 3*(1/1.8432 MHz) or 1.63 s.
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HSDL-7002 Package Dimensions
Figure 3. HSDL-7002 Package Dimensions
b Min. Nom. Max. 16L 0.25 0.28 0.33
N
D2 Min. Nom. Max. 2.05 2.10 2.15
E2 e L JEDE Min. Nom. Max. Min. Nom. Max. 2.05 2.10 2.15 0.650 BSC. 0.55 0.60 0.65 MO-220VGGC
Symbol A A1 A3 D E JEDEC 3.85 3.85 0.00
Dimension in mm Minimum Nominal 0.80 0.02 0.20 REF. 4.00 4.00 4.15 4.15 0.152 0.152 MO-220 Maximum 0.84 0.04 0.00
Dimension in inch Minimum Nominal 0.031 0.0008 0.008 REF. 0.157 0.157 0.163 0.163 Maximum 0.033 0.0015
PIN ASSIGNMENT PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 /TXD RXD A0 A1 A2 CLK_SEL GND /NRST PIN 9 PIN 10 PIN 11 PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 /IR_RXD IR_TXD PULSEMOD POWERDN OSCOUT OSCIN VCC 16XCLK
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HSDL-7002 Tape Dimensions
HSDL-7002 Reel Dimensions
"B" "C" Quantity 330 80 2500
Unit: mm
Detail A 2.0 0.5 13.0 0.5 B C
R1.0 LABEL 21 0.8
Detail A
16.4
+2 0
2.0 0.5
6
HSDL-7002 Moisture Proof Packaging
All HSDL-7002 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC MSL (Moisture Sensetive Level ) 3.
Recommended Storage Conditions
Storage Temperature 10C to 30C Relative Humidity below 60% RH
Time from unsealing to soldering
After removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions. If times longer than three days are needed, the parts must be stored in a dry box.
Baking Conditions
If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Package In reels In bulk Temp 60 C 100 C 125 C 150 C Baking should only be done once. Time 48hours 4hours 2 hours 1 hour
Units in A Sealed Moisture-Proof Package
Package Is Opened (Unsealed)
Environment less than 25 deg C, and less than 60% RH Yes
No Baking Is Necessary
Yes
Package Is Opened for less than 168 hours No
Perform Recommended Baking Conditions
No
Figure 4. Baking Conditions Chart
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Recommended Reflow Profile
255 T - TEMPERATURE (C) 230 220 200 180 160 120 80 25 0 P1 HEAT UP 50 100 P2 SOLDER PASTE DRY 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300 t-TIME (SECONDS) R1 MAX 260C R3 R4
R2
60 sec MAX Above 220 C
R5
Process Zone Heat Up Solder Paste Dry Solder Reflow
Symbol P1, R1 P2, R2 P3, R3P3, R4
DT 25C to 160C 160C to 200C 200C to 255C (260C at 10 seconds max) 255C to 200C 200C to 25C
Maximum DT/Dtime 4C/s 0.5C/s 4C/s-6C/s
Cool Down
P4, R5
-6C/s
The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. TheDT/Dtime rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-7002 castellation pins are heated to a temperature of 160C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4C per second to allow for even heating of both the PC board and HSDL-7002 castellations. Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200C (392F).
Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255C (491F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200C (392F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed 6C per second maximum. This limitation is necessary to allow the PC board and HSDL-7002 castellations to change dimensions evenly, putting minimal stresses on the HSDL7002 endec.
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Appendix A: General Application Guide for the HSDL-7002 Application Circuits for HSDL-7002
HSDL-3201 HSDL-7002 UART 16550
TXD
IR_TXD
TXD RXD
SOUT SIN BAUDOUT
RXD RXD
IR_RXD
16XCLK NRST 10 k 0.1 uF
Vcc
Figure 5. HSDL-7002 Connection between a standard 16550 UART and HSDL-3201
HSDL-3201 HSDL-7002 TXD TXD IR_TXD RXD A0 A1 A2 CLK_SEL PULSEMOD POWERDN OSCOUT NRST 10 k Vcc 10 M 15 pF F = 3.6864 MHz 0.1 uF MICRO CONTROLLER SD0 SD1 IO1 IO2 IO3 IO4 IO5 IO6
RXD
RXD
IR_RXD OSCIN
15 pF
Note: POWERDN can be used as a basic chip select. The HSDL-7002 will not be able to receive or transmit data while POWERDN is asserted.
Figure 6. HSDL-7002 Connection between a Microcontroller and HSDL-3201
Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps) 115200 57600 19200 9600 38400 4800 2400 A2 A1 A0 Crystal Freq. Division Divided by 2 Divided by 4 Divided by 12 Divided by 24 Divided by 6 Divided by 48 Divided by 96
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
Encoding Scheme
The encoding scheme relies on a clock being present, which is set to 16 times the data transmission baud rate (16XCLK). The encoder sends a pulse for every space or "0" that is sent on the TXD line. On a high to low transition of the TXD line, the generation of the pulse is delayed for 7 clock cycles of the 16XCLK before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. This generates a 3/16th bit time pulse centered around the bit of information ("0") that is being transmitted. For consecutive spaces, pulses with a 1 bit time delay are generated in series. If a logic "1" (mark) is sent then the encoder does not generate a pulse.
Decoding Scheme
The IrDA-SIR decoding modulation method can be thought of as a pulse-stretching scheme. Every high to low transition of the IR_RXD line signifies the arrival of a pulse. This pulse needs to be stretched to accommodate 1 bit time (or 16 16XCLK cycles). Every pulse that is received is translated into a "0" or space on the RXD line equal to 1 bit time.
16 CYCLES 16XCLK
16 CYCLES
16 CYCLES
16 CYCLES
TXD
IRTXD
7 CS
3 CS
Figure 7. HSDL-7002 Encoding Scheme
16 CYCLES 16XCLK
16 CYCLES
16 CYCLES
16 CYCLES
IRRXD
3 CS
RXD
Figure 8. HSDL-7002 Decoding Scheme
Notes: 1. The stretched pulse must be at least 3/4 of a bit time in duration to be correctly interpreted by a UART. 2. It is recommended that the TXD remains high when not transmitting. This ensures the LED is off and will not interfere with signal reception.
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Monoshot Operation
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CRYSTAL CLK
INT CLK (DIV BY 2) TXD
INTERNAL IRTXD OUTPUT
IRTXD (MONOSHOT)
6 CRYSTAL CYCLES
The figure above illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e., when A2=0, A1=0, and A0=0. A rising edge on the internal modulation state machine (IR_TXD output), will cause the output on the IR_TXD to go up for 6 crystal clock cycles. With a 3.6864 MHz clock, this corresponds to a pulse of 1.63 s. The duration of this pulse is independent of the code A2, A1, A0 and is always 6 clock cycles of the crystal, corresponding to the monoshot operation.
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Data subject to change. Copyright (c) 2007 Lite-On Technology Corporation. All rights reserved.

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